Conventionally, compact discs (CD) have been broadly used on which digital audio data having a sampling frequency fs of approximately 44.1 kHz with each sample having 16 bits for each channel are recorded. On the other hand, super audio compact discs (SACD) generated by the DSD (direct stream digital) system have been proposed on which audio stream data of the 1-bit system having a very high sampling frequency, for example, a frequency which is 64 times the sampling frequency fs of an ordinary CD, are recorded.
As will be described later, as over-sampling and ΔΣ modulation with 64 fs are performed on an input signal, a 1-bit audio digital signal is obtained. In a system of the CD format, decimation from a 1-bit signal to a multi-bit PCM code is carried out immediately after that, whereas on a SACD employing the DSD system, a 1-bit audio signal is directly recorded.
An audio data reproducing device for reproducing a 1-bit audio signal from a SACD will now be described. This audio data reproducing device has a structure as shown in FIG. 1.
On a SACD 1 from which data is reproduced by the audio data reproducing device shown in FIG. 1, a 1-bit audio signal is directly recorded as described above. The 1-bit audio signal recorded on the SACD 1 is generated by a ΔΣ modulator based on the DSD system as shown in FIG. 2. In the ΔΣ modulator, an adder 121 calculates a differential signal between the input signal as an audio signal inputted through an input terminal 120 and a 1-bit pulse string, and an integrator 122 integrates the differential signal. In this case, an audio band error is extracted. A process of converting this signal to a 1-bit pulse output by a quantizer 123 and feeding back the error again is repeated many times. Thus, a 1-bit audio signal is generated.
The SACD 1, on which the 1-bit audio signal is recorded, is mounted on a disc table of the audio data reproducing device shown in FIG. 1 and is rotated, for example at a constant linear velocity by a spindle motor, not shown. The SACD 1, which is being rotated, is irradiated with a reproducing laser beam emitted from an optical pickup 102 and the 1-bit audio signal is read out from the SACD 1. The optical pickup 102 is moved between the inner and outer circles of the SACD 1 by a feed mechanism, not shown, and thus scans the signal recording area of the SACD 1 with the reproducing laser beam to read the 1-bit audio signal recorded on the SACD 1.
The signal read out by the optical pickup 102 is supplied to an RF amplifier 103. An RF signal outputted from the RF amplifier 103 is supplied to a front-end processor unit 104. The front-end processor unit 104 uses an external memory 105 as a buffer for data or as a work area during error correction processing. The front-end processor unit 104 performs demodulation and error correction processing on the RF signal to generate sector data with a fixed length of 2064 bytes and supplies the sector data toe an audio decoder unit 106 on the subsequent stage.
The audio decoder unit 106 receives, by 1 byte each, the sector data of a fixed length of 2064 bytes supplied from the front-end processor unit 104. In the audio decoder unit 106, an audio header starting at, for example, the 13th byte from the leading part of each sector is analyzed by an audio header analyzer 111 and the data is recorded by frame into each block of an external memory 107, with each frame having 1/75 seconds.
The data recorded by frame in each block of the external memory 107 is decoded by a compression decoder 112 inside the audio decoder unit 106. After that, fader processing is performed on the data by a fader 113, when necessary, and the data is then converted to an analog audio signal by a D/A converter 108. The analog audio signal is supplied to an external amplifier, a speaker and the like through an output terminal 109.
When the data is recorded by frame into each block of the external memory 107 with each frame having 1/75 seconds while the audio header analyzer 111 analyzes the audio header, areas for recording an audio frame (FA) formed by connecting audio packets and a supplementary frame (FS) formed by connecting supplementary packets in the sector recorded in the external memory 105 shown in FIG. 3 are also separated in each block of the external memory 107 shown in FIG. 4. A padding packet and stuffing data shown in FIG. 3 are not recorded in each block, as shown in FIG. 4. The purpose of classifying the data by type into audio data and supplementary data and buffering the data by frame (FA, FS) in FIG. 4 is to quickly send the data to the compression decoder 112 on the subsequent stage which requests only frame-based audio data.
In each frame shown in FIG. 4, data is recorded with frame information added thereto, the frame information consisting of error information and a time code. The error information indicates that a frame including data which could not be error-corrected by the front-end processor unit 104 is an error frame. Since the time code is incremented by frame, discontinuity of frames can be detected by comparing the preceding and subsequent time codes.
The audio decoder unit 106 reads in advance the frame information IF recorded in the external memory 107 and therefore can send an error flag to the fader 113 before outputting a discontinuous point of frames due to an error frame, cue/review and tune selection, or the last data of the final frame in which recording is completed in the buffer, as a SDS signal. Therefore, the fader 113 can perform gradually attenuated fade-out processing on the DSD output, thus preventing occurrence of a strange sound.
In this manner, in the audio data reproducing device having the structure as shown in FIG. 1, the front-end processor unit 104 and the audio decoder unit 106 need the external memory 105 and the external memory 107, respectively.
Meanwhile, on the assumption that an IC for the front-end processor unit 104 and an IC for the audio decoder unit 106 are collectively provided on one chip in the above-described audio data reproducing device shown in FIG. 1, if a single external memory is used instead of the external memories 105 and 107 which are conventionally used by the front-end processor unit 104 and the audio decoder unit 106, respectively, there are advantages such as reduction in cost, reduction in power consumption, decrease in the number of IC pins and reduction in the board area.
If the conventional function of the external memory 105 connected to the front-end processor unit 104 and the function of the external memory 107 connected to the audio decoder unit 106 are to be provided in a new single memory by dividing the area of the memory on the basis of the address, as shown in FIG. 5, the frame state will be buffered after buffering of the sector status, and therefore the number of accesses to the memory increases. To guarantee the number of accesses, the frequency of a block for generating a control signal of the memory must be raised or the circuit within the IC must operate at high speed. Moreover, the priority control for the access right to the memory is complicated and the number of accesses to continuous addresses is reduced. Therefore, the advantage of the high-speed page mode cannot be fully utilized.